1. Field of the Invention
The present invention relates to a cell characteristic measuring circuit formed on a semiconductor wafer to measure the characteristics of cell transistors in a memory cell array, and a cell characteristic measuring method.
2. Description of the Related Art
In an EEPROM and EPROM, transistors each include a stacked gate structure having a floating gate and control gate stacked with an insulating film provided relative to a substrate. The transistor has a threshold voltage value in accordance with memory information "1" and "0".
In the cell transistor having a stacked gate structure as set out above, if electric charges are stored in the floating gate, then there occurs a rise in a threshold level and hence a decrease in a cell current in a cell transistor. On the other hand, if the electric current is drawn out of the floating gate, then there occurs a fall in the threshold value and hence an increase in the cell current.
A reading circuit for reading memory contents out of the cell transistors is comprised of a combination of a sense amplifier circuit and load circuit for converting a cell current to a voltage. With "0" data representing cell memory information at a threshold value exceeding a given reference voltage of determination and "1" data, cell memory information at the threshold value not exceeding the given reference voltage of determination, the reading circuit performs a read-out operation after the conversion of the memory information of cells to continuous digital memory information.
In the development of a nonvolatile memory, various characteristics of cell transistors are determined and evaluated for their reliability. For the measurement and evaluation, there are many checking items, such as the measurement of the static characteristics of the cell transistors, write/erase characteristics, data retaining characteristics, threshold value distribution, etc. The cell transistors manufactured under various process conditions are measured and evaluated to enable an optimal condition to be determined and a cause for defects to be analyzed.
These evaluations are conducted on the individual memory cells, but those cells in a memory cell array may be variously influenced in a different way from the individual cells. Since it is necessary to measure the variation of the characteristics among cells in a large quantity, it is important to measure the characteristics of the arrayed memory cells.
In order to measure the arrayed cell transistors for their static characteristics, a cell array 80 of a simple structure is formed on a test element group (TEG) area on a semiconductor wafer as shown in FIG. 11. In the cell array TEG area, word line WLi (i=1, 2, . . . ), bit lines BLi (i=1, 2 . . . ), common source line CS, etc., are connected to many external terminals (pads) 81. Those cell transistors, corresponding to the product of the number of word line on the pads times the number of bit line on the pads, are measured for their characteristics.
In comparison with measuring characteristics of cell transistors using a memory circuit, if a cell array TEG area is used, it is possible to freely set word line voltages of the cell transistors and to directly measure cell currents of the cell transistors, though being less in the number of their measurable bits. It is, therefore, possible to make measurements with a greater latitude. Further, the cell array TEG area can be formed simply through the formation process of the cell transistors, thus ensuring a shorter period of manufacture as well as high efficiency in development.
It is to be noted, however, that the memory circuit is used for reliability evaluation necessary to the measurement of cells in a large quantity, such as the threshold value distribution of the cell transistors and data retaining characteristics.
For the measurement of the cell array TEG area, checking items are restricted for evaluation and, further, the number of measurable cells corresponds to the product of the number of word lines on pads times the number of bit lines on the pads. If this is the case, the practical limit is on the order of a few hundred. In the case where those items for reliability evaluation have a probability of one in a few M bits (or more), it is possible to measure only a few hundred, so that no correct evaluation is conducted. For the evaluation of threshold value distribution, the items measurable at this time are too small in number in view of being on the order of a few hundred bits.
On the other hand, the reliability evaluation using the memory circuit is low in the freedom with which word line voltages are set. Further, it is difficult to negatively bias the word lines, so that a negative threshold value cannot be readily set. In order to enable the word lines to be biased negatively, an associated circuit arrangement, including a word line decoder circuit, etc., becomes very complicated.
In the reliability evaluation, defective cells are detected with a probability of one in a few M bits (or more) and, in this case, it is sometimes desirable to further measure such a defective cell for its detailed characteristics, such as the static characteristic. For the more detailed individual characteristics as set out above, it is not possible to measure the cell transistors individually, for the detailed characteristics, with the use of the cell array TEG alone, while, on the other hand, evaluating the cell transistors, for reliability, with the use of the memory circuit.
Further, in order to effect reliability evaluation with the memory circuit, the memory circuit has to be fabricated with a full process including the manufacturing step of a high withstand transistors, etc., thus resulting in a prolonged term of fabrication and a lowered efficiency of evaluation. Many input signals are required in a timed way to an associated circuit and the measurement as set out above cannot be made with a low-speed DC tester of such a type as to measure a simple TEG area alone. Since the measurement needs to be conducted with an LSI tester high in costs and complicated in operation, the evaluation efficiency is lowered.
As already set out above, the conventional measurement using the cell array TEG cannot be conducted for the reliability evaluation of the cell array, while, on the other hand, the reliability evaluation using the memory circuit cannot measure the detailed characteristic on those defective cells detected, such as the static characteristic. It is, therefore, necessary to, for measurement, use an expensive LSI tester involving a complicated operation.